Digital Circuits Lecture-67: 3-bit Synchronous DOWN Counter using JK-FF

In this lecture, i discussed how to design 3-bit or MOD-8 synchronous up counter using JK-FF.

For Video Lecture follow the below link:  
https://youtu.be/8CRWN_0RGyU

For Lecture Material download from follow the below link:
http://www.mediafire.com/file/p1xa3bucghzh1yc/DE-Lec-67.pdf